(1) Field of the Invention
This invention relates generally to voltage regulators, and more particularly to an enhancement of low dropout voltage regulators having an adaptive biased driving stage in order to improve stability through a very wide range of output current.
(2) Description of the Prior Art
Low-dropout (LDO) linear regulators are commonly used to provide power to low-voltage digital and analog circuits, where point-of-load and line regulation is important. FIG. 1 prior art shows a typical basic circuit of a LDO regulator 3 having an input voltage Vi 1, an output voltage Vo 2, an input current Ii and an output current Io.
Conventional LDO regulators are very problematic in the area of transient response. Transient response is the behavioral of the regulator after a abrupt change of either the load current (load response) or the input voltage (line response). A minimum under and overshoot of the regulated voltage and a fast settling is desired. The transient response is defined by the frequency compensation of the regulation loop. Voltage regulators are difficult to compensate because of the fact that the load resistance and with this the output pole can vary over a wide range. For zero load the load resistance is infinite and the output pole is zero Hz. For maximum load the load resistance is at its minimum and the output pole is as its maximum, that might be a few KHz.
Said frequency compensation is still a challenge for the designers of LDO regulators
U.S. Patent (U.S. Pat. No. 6,246,221 to Xi.) describes a high power supply ripple rejection (PSRR) internally compensated low drop-out (LDO) voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator.
FIG. 2 prior art shows a simplified circuit of an embodiment of a PMOS LDO according to said U.S. Pat. No. 6,246,221 to Xi. Said regulator is a multiple-loop regulator. Said circuit comprises a gm-buffer amplifier 202 to push the gate pole of the PMOS pass device 201 to high frequencies. Transistor 203 serves for adaptive biasing the gm-buffer amplifier 202. 211 represents the equivalent series resistance (ESR) of the load capacitor 213. 212 represents the equivalent series inductance (ESL) of the load capacitor 213. In case of low loads the out-pole formed by the load capacitor 213 and the load resistance 210 goes to low frequencies and thus it is possible to lower the gate-pole also.
In the U.S. patent application Ser. No. 10/347,983, filed on Jan. 21, 2003, a LDO is described having an error amplifier as part of a current mirror output stage. A method and a circuit to achieve a low dropout voltage regulator having a constant high performance under all operating conditions, including the dropout region, has been disclosed in said patent application. A regulated cascade structure is placed at the input of a current mirror and in connection with a voltage regulator output stage. In contrast to other applications the positive input of the error amplifier is not biased with a reference voltage but connected to the regulator output. Therefore the cascade structure regulates the voltage of the entry node of the current mirror to be equal to the output voltage of the regulator under all operating conditions of the regulator. Thus the transistors of the current mirror have always identical drain-source voltages. Therefore the regulator is kept in the optimal, balanced operating point, a constant high regulator loop gain is achieved and PSRR and load regulation performance is no more reduced under dropout operating conditions.
FIG. 3 prior art shows a simplified circuit of an embodiment of a LDO according to said U.S. patent application Ser. No. 10/347,983, filed on Jan. 21, 2003. 302 is the input transistor of a current mirror formed by PMOS pass device 301 and said input transistor 302. Equivalent to FIG. 2 prior art 311 represents the equivalent series resistance (ESR) of the filter capacitor 313. 312 represents again the equivalent series inductance (ESL) of the filter capacitor 313. 310 represents the load resistance of said LDO again. In said embodiment the gate-pole of the PMOS pass device 301 moves in a constant ratio with the out-pole. Said gate-pole of the pass device is formed by the gate capacity Cgate of transistor 301 and 1/gm of the input transistor 302, wherein gm represents the transconductance gain of transistor 302. Said out-pole is formed by the load resistance 310 and the load capacitor 313.
There are additional patents dealing with the stabilization of LDOs.
U.S. Patent Application Publication 2002/0130646 (to Zadeh et al.) describes a linear voltage regulator, such as a low-dropout regulator, supplying power to one or more digital circuits within a computer system. The low-dropout regulator provides a substantially constant output voltage independent of loading conditions. The low-dropout regulator is biased at a relatively low operating current for steady-state operation to improve power efficiency of the low-dropout regulator. During a loading condition change, an adaptive biasing circuit senses the loading condition change and provides additional biasing current to momentarily increase the operating current of the low-dropout regulator to improve transient response.